The present invention relates to semiconductor design technology, and more particularly, to a delay locked loop circuit of a semiconductor device.
A synchronous semiconductor memory device such as a DDR SDRAM (Double Data Rate Synchronous DRAM) transmits data to external devices using an internal clock that is synchronized with an external clock inputted from an external device such as a memory controller CTRL.
In order to stably transmit data between a memory and a memory controller, it is important to synchronize data outputted from the memory with an external clock supplied from the memory controller to the memory.
A memory outputs data synchronized with an internal clock. Even if the internal clock is synchronized with an external clock when the internal clock is supplied to the memory, the internal clock may be delayed while passing through components of the memory. Therefore, when the internal clock is outputted, the internal clock may become desynchronized.
Therefore, it is necessary to synchronize the internal clock with the external clock. The internal clock is compensated for a time taken for data to travel along a bus in order to accurately place the delayed internal clock at an edge or a center of the external clock supplied from a memory controller.
In order to compensate for the delayed internal clock, a clock synchronizing circuit was introduced. The clock synchronizing circuit includes a phase locked loop circuit (PLL) and a delay locked loop circuit (DLL).
Between the phase locked loop (PLL) circuit and the delay locked loop (DLL) circuit, the phase locked loop (PLL) circuit is used when a frequency of an internal clock is different from that of an external clock because the phase locked loop (PLL) circuit can multiply a frequency. When the internal clock and the external clock have the same frequency, the delay locked loop circuit (DLL) is generally used because the delay locked loop circuit (DLL) is less sensitive to noise and occupies comparatively small area.
Since the internal clock and the external clock have the same frequency in case of a semiconductor memory device, the delay locked loop (DLL) circuit is generally used for the semiconductor memory device as the clock synchronizing circuit. For a semiconductor memory device, a register-controlled delay locked loop DLL circuit is widely used due to following advantages. The register-controlled delay locked loop (DLL) circuit includes a register for storing a locked delay value. The register-controlled delay locked loop circuit stores the locked delay value in the register when power is interrupted. After the power is supplied again, the register-controlled delay locked loop circuit loads and uses the stored delay value to lock the internal clock. Therefore, a semiconductor memory device can start clock synchronization with a comparatively small phase difference between the internal clock and the external clock when the semiconductor memory device performs an initial operation. After the initial operation, the register-controlled delay locked loop circuit can control a variable range of a delay value stored in the register according to a phase difference between the internal clock and the external clock. Therefore, the register-controlled delay locked loop circuit can synchronize the internal clock and the external clock in comparatively short time.
FIG. 1 is a block diagram illustrating a register-controlled delay locked loop (DLL) circuit according to the related art.
Referring to FIG. 1, the register-controlled delay locked loop (DLL) circuit according to the related art includes a phase comparator 100, a clock delay 120, and a delay replica model 140. The phase comparator 100 compares a phase of a source clock REFCLK with a phase of a feedback clock FBCLK and generates a delay locking signal DELAY_LOCK_CTRL corresponding to the comparison result. The clock delay 120 delays the source clock REFCLK in response to a delay locking signal for locking delay and outputs the delayed clock as a delay locked clock DLLCLK. The delay replica model 140 reflects a delay time of an output path of the source clock REFLCK at the delay locked clock DLLCLK and outputs the reflected clock as a feedback clock FBCLK.
Hereinafter, a delay locking operation of the register control delay locked loop circuit according to the related art will be described with reference to FIG. 1. Before locking, a phase of a source clock REFCLK does not match that of a feedback clock FBCLK. The register control delay locked loop circuit delays the phase of the source clock REFCLK and outputs the delay source clock as a delay locked clock DLLCLK in order to synchronize a reference edge of the source clock REFCLK with a reference edge of a feedback clock FBCLK. Here, the reference edge of the source clock REFCLK is generally a rising edge. However, the reference edge may be a falling edge. Since the delay locked clock DLLCLK is reflected with the delay condition of a source clock path and outputted as the feedback clock FBCLK, the phase difference between the source clock REFCLK and the feedback clock FBCLK is gradually reduced by increasing a delay amount for delaying a phase of the source clock REFCLK.
However, the register-controlled delay locked loop (DLL) circuit according to the related art is set up with a maximum delay amount that can be applied until outputting the delay locked clock DLLCLK by delaying the phase of the source clock REFCLK. If the phase of the source clock REFCLK is not synchronized with the phase of the feedback clock FBCLK before the maximum delay amount is applied, the register-controlled delay locked loop (DLL) circuit according to the related art may not be able to terminate a delay locking loop operation.